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參數(shù)資料
| 型號： | MM54HC165J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | HC/UH SERIES, 1-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 136K |
| 代理商： | MM54HC165J |
TLF5316
MM54HC165MM74HC165
Parallel-inSerial-out
8-Bit
Shift
Register
January 1988
MM54HC165MM74HC165
Parallel-inSerial-out 8-Bit Shift Register
General Description
The MM54HC165MM74HC165 high speed PARALLEL-IN
SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-
gate CMOS technology It has the low power consumption
and high noise immunity of standard CMOS integrated cir-
cuits along with the ability to drive 10 LS-TTL loads
This 8-bit serial shift register shifts data from QA to QH when
clocked Parallel inputs to each stage are enabled by a low
level at the SHIFTLOAD input Also included is a gated
CLOCK input and a complementary output from the eighth
bit
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a CLOCK INHIBIT function
Holding either of the CLOCK inputs high inhibits clocking
and holding either CLOCK input low with the SHIFTLOAD
input high enables the other CLOCK input Data transfer
occurs on the positive going edge of the clock Parallel load-
ing is inhibited as long as the SHIFTLOAD input is high
When taken low data at the parallel inputs is loaded directly
into the register independent of the state of the clock
The 54HC74HC logic family is functionally as well as pin-
out compatible with the standard 54LS74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground
Features
Y
Typical propagation delay 20 ns (clock to Q)
Y
Wide operating supply voltage range 2 – 6V
Y
Low input current 1 mA maximum
Y
Low quiescent supply current 80 mA maximum
(74HC Series)
Y
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TLF5316 – 1
Top View
Order Number MM54HC165 or MM74HC165
Function Table
Inputs
Internal
Output
Shift
Clock
Clock Serial
Parallel
Outputs
QH
Load Inhibit
A
H QA
QB
L
X
a
h
a
b
h
HL
L
X
QA0 QB0
QH0
HL
u
HX
H
QAN
QGN
HL
u
LX
L
QAN
QGN
HH
X
QA0 QB0
QH0
H e High Level (steady state) L e Low Level (steady state)
X e Irrelevant (any input including transitions)
u e Transition from low to high level
QA0 QB0 QH0 e The level of QA QB orQH respectively before the
indicated steady-state input conditions were established
QAN QGN e The level of QA or QG before the most recent
u transition of
the clock indicates a one-bit shift
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM74HC166N | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| MM54HC166N | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| MM74HC173MX | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| MM74HC173N | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| MM74HC174J | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM54HC166 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Parallel In/Serial Out Shift Registers |
| MM54HC173 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI - STATE-R QUAD D FLIP-FLOP |
| MM54HC173 WAF | 制造商:Texas Instruments 功能描述: |
| MM54HC173J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI - STATE-R QUAD D FLIP-FLOP |
| MM54HC174J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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