
Using the CMOS Dual
Monostable Multivibrator
INTRODUCTION
The MM54C221/MM74C221 is a dual CMOS monostable
multivibrator. Each one-shot has three inputs (A, B and CLR)
and two outputs (Q and Q ). The output pulse width is set by
an external RC network.
The A and B inputs trigger an output pulse on a negative or
positive input transition respectively. The CLR input when
low resets the one-shot. Once triggered the A and B inputs
have no further control on the output.
THEORY OF OPERATION
Figure 1 shows that in its stable state, the one-shot clamps
C
to ground by turning N1 ON and holds the positive
comparator input at V
by turning N2 OFF. The prefix N is
used to denote N-channel transistors.
The signal, G, gating N2 OFF also gates the comparator
OFF thereby keeping the internal power dissipation to an ab-
solute minimum. The only power dissipation when in the
stable state is that generated by the current through R
.
The bulk of this dissipation is in R
since the voltage drop
across N1 is very small for normal ranges of R
EXT
.
To trigger the one-shot the CLR input must be high.
The gating, G, on the comparator is designed such that the
comparator output is high when the one-shot is in its stable
state. With the CLR input high the clear input to FF is dis-
abled allowing the flip-flop to respond to the A or B input. A
negative transition onAor a positive transition on B sets Q to
a high state. This in turn gates N1 OFF, and N2 and the com-
parator ON.
Gating N2 ON establishes a reference of 0.63 V
CC
on the
comparator’s positive input. Since the voltage on C
can
not change instantaneously V1 = 0V at this time. The com-
parator then will maintain its one level on the output. Gating
N1 OFF allows C
EXT
to start charging through R
EXT
toward
V
CC
exponentially.
Assuming a perfect comparator (zero offset and infinite gain)
when the voltage on C
, V1, equals 0.63 V
the com-
parator output will go from a high state to a low state reset-
ting Q to a low state. Figure 2 is a timing diagram summariz-
ing this sequence of events.
This diagram is idealized by assuming zero rise and fall
times and zero propagation delay but it shows the basic op-
eration of the one-shot. Also shown is the effect of taking the
CLR input low. Whenever CLR goes low FF is reset indepen-
dent of all other inputs. Figure 2 also shows that once trig-
gered, the output is independent of any transitions on B (or
A) until the cycle is complete.
Fairchild Semiconductor
Application Note 138
May 1975
U
A
1998 Fairchild Semiconductor Corporation
AN006023
www.fairchildsemi.com