參數(shù)資料
型號: MM54C175J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 鎖存器
英文描述: CMOS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 3/6頁
文件大?。?/td> 114K
代理商: MM54C175J
AC Electrical Characteristics TA e 25 C CL e 50 pF unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd
Propagation Delay Time to
VCC e 5V
190
300
ns
a Logical ‘‘0’’ or Logical ‘‘1’’ from
VCC e 10V
75
110
ns
Clock to Q or Q
tpd
Propagation Delay Time to a
VCC e 5V
180
300
ns
Logical ‘‘0’’ from Clear to Q
VCC e 10V
70
110
ns
tpd
Propagation Delay Time to a
VCC e 5V
230
400
ns
Logical ‘‘1’’ from Clear to Q
VCC e 10V
90
150
ns
tS
Time Prior to Clock Pulse that
VCC e 5V
100
45
ns
Data Must be Present
VCC e 10V
40
16
ns
tH
Time After Clock Pulse that
VCC e 5V
0
b
11
ns
Data Must be Held
VCC e 10V
0
b
4ns
tW
Minimum Clock Pulse Width
VCC e 50V
130
250
ns
VCC e 10V
45
100
ns
tW
Minimum Clear Pulse Width
VCC e 50V
120
250
ns
VCC e 10V
45
100
ns
tr
Maximum Clock Rise Time
VCC e 5V
15
450
m
s
VCC e 10V
50
125
m
s
tf
Maximum Clock Fall Time
VCC e 5V
15
50
m
s
VCC e 10V
50
m
s
fMAX
Maximum Clock Frequency
VCC e 5V
20
35
MHz
VCC e 10V
50
10
MHz
CIN
Input Capacitance
Clear Input (Note 2)
10
pF
Any Other Input
50
pF
CPD
Power Dissipation Capacitance
Per Package (Note 3)
130
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2
Capacitance is guaranteed by periodic testing
Note 3
CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C74C Family Characteristics Application Note
AN-90
Switching Time Waveforms
CMOS to CMOS
TLF5900 – 6
3
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