參數(shù)資料
型號: ML9475
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 顯示控制器
英文描述: DOT MAT LCD DRVR AND DSPL CTLR, PQFP56
封裝: 0.65 MM PITCH, PLASTIC, QFP-56
文件頁數(shù): 2/20頁
文件大?。?/td> 267K
代理商: ML9475
FEDL9475-01
ML9475
10/20
POWER-ON/OFF TIMING
If LVDD is in the range of 0 V to LVDDmin, make sure that LVDD
≥ DVDD and t ≥ 0[ns] are satisfied.
When performing power-on reset with a capacitor connected to the
RESET pin, be careful about the relationship
between the capacitance value and the rise time of the power supply.
INITIALIZATION TIMING
Drive the
RESET pin Low and hold it Low under the condition “t1 ≥ 0[ns]” until LVDD reaches LVDDmin.
The value of the current of the pull-up resistor is specified for
RESET pin.
The customer needs to select an external capacitor that meets the timing requirements shown above.
LVDD
DVDD
Time
Voltage
t
LVDD
RESET
VIL
t1
LVDDmin
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