參數(shù)資料
型號(hào): ML9042-21CVWA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 顯示控制器
英文描述: 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
封裝: DIE-233
文件頁數(shù): 3/58頁
文件大?。?/td> 558K
代理商: ML9042-21CVWA
FEDL9042-01
OKI Semiconductor
ML9042-xx
11/58
I/O Characteristics
Parallel Interface Mode
The timing for the input from the CPU and the timing for the output to the CPU are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.7 to 4.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS0/CSB, RS1 Setup Time
tB
40
ns
E/SHTB Pulse Width
tW
450
ns
RW/SI, RS0/CSB, RS1 Hold Time
tA
10
ns
E/SHTB Rise Time
tr
125
ns
E/SHTB Fall Time
tf
125
ns
E/SHTB Pulse Width
tL
430
ns
E/SHTB Cycle Time
tC
1000
ns
DB0(SO) to DB7 Input Data Setup Time
tI
195
ns
DB0(SO) to DB7 Input Data Hold Time
tH
10
ns
(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS0/CSB, RS1 Setup Time
tB
40
ns
E/SHTB Pulse Width
tW
220
ns
RW/SI, RS0/CSB, RS1 Hold Time
tA
10
ns
E/SHTB Rise Time
tr
125
ns
E/SHTB Fall Time
tf
125
ns
E/SHTB Pulse Width
tL
220
ns
E/SHTB Cycle Time
tC
500
ns
DB0(SO) to DB7 Input Data Setup Time
tI
60
ns
DB0(SO) to DB7 Input Data Hold Time
tH
10
ns
RS1, RS0/CSB
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
RW/SI
E/SHTB
DB0(SO) to DB7
tL
tB
tW
tr
tf
tA
tH
tI
Input
Data
tC
相關(guān)PDF資料
PDF描述
ML9042-01CVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
ML9042-11DVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
ML9042-11CVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
ML9042-21DVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233
ML9044-51BCVWA 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175
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