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參數(shù)資料
| 型號： | ML9042-01DVWA |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
| 封裝： | DIE-233 |
| 文件頁數(shù)： | 24/58頁 |
| 文件大小： | 558K |
| 代理商： | ML9042-01DVWA |
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FEDL9042-01
OKI Semiconductor
ML9042-xx
30/58
Instruction Codes
Table of Instruction Codes
Code
Instruction
RS1
RS0/
CSB
RW/
SI
DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
(SO)
Function
Execution
Time
f = 270 kHz
Display Clear
1
0
1
Clears all the displayed digits of the
LCD and sets the DDRAM address 00
in the address counter. The arbitrator
data is cleared.
1.52 ms
Cursor Home
1
0
1
X
Sets the DDRAM address 00 in the
address counter and shifts the display
back to the original. The content of the
DDRAM remains unchanged.
1.52 ms
Entry Mode
Setting
1
0
1
I/D
S
Determines the direction of movement
of the cursor and whether or not to shift
the display. This instruction is
executed when data is written or read.
37
s
Display
ON/OFF Control
1
0
1
D
C
B
Sets LCD display ON/OFF (D), cursor
ON/OFF (C) or cursor-position
character blinking ON/OFF (B).
37
s
Cursor/Display
Shift
1
0
1
S/C R/L
X
Moves the cursor or shifts the display
without changing the content of the
DDRAM.
37
s
Function Setting
1
0
1
DL
N
ABE SSR CSR
Sets the interface data length (DL), the
number of display lines (N), the
arbitrator display (ABE), the segment
data shift direction (SSR), or the
common data shift direction (CSR).
37
s
CGRAM
Address Setting
1
0
1
ACG
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.
37
s
DDRAM
Address Setting
1
0
1
ADD
Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.
37
s
Busy Flag/
Address Read
1
0
1
BF
ADC
Reads the Busy Flag (indicating that
the ML9042 is operating) and the
content of the address counter.
0
s
RAM Data Write
1
0
WRITE DATA
Writes data in DDRAM, ABRAM or
CGRAM.
37
s
RAM Data Read
1
READ DATA
Reads data from DDRAM, ABRAM or
CGRAM.
37
s
Arbitrator
Display Line Set
0
1
AS Sets the arbitrator display line.
37
s
ABRAM
Address Setting
0
1
AAB
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
37
s
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| ML9042-01DVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
| ML9042-11DVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ML9042-54CVWA-5016 | 制造商:ROHM Semiconductor 功能描述:RHOML9042-54CVWA-5016 OKI LCD DRIVER |
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