參數(shù)資料
型號(hào)： ML9041-XXBCVWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 顯示控制器
英文描述： 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175
封裝： 10.62 X 2.55 MM, GOLD BUMP, DIE-175
文件頁(yè)數(shù)： 15/61頁(yè)
文件大?。?/td> 572K
代理商： ML9041-XXBCVWA
PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
21/60
Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address area is 00 to 19
(00H to 13H).
Although an address exceeding 19 (13H) can be set or the address already set may exceed it due to automatic
increment or decrement processing, any address out of the valid address area is ignored.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
MSB
LSB
DB
6 DB5 DB4 DB3 DB2 DB1 DB0
Hexadecimal
ADC
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.
The arbitrator display is not shifted by any instructions and has the following relationship with the LCD display
positions.
*
E4 E3 E2 E1
E0
DB
6
*
DB
7
DB
5 DB4 DB3 DB2 DB1 DB0
* Don’t Care
Display - ON data
E4
5XSn+1
5XSn+5
Configuration of input display data
Input data
Relationship between display-ON
data and segment pins
Sn = AB RAM address (0 to 19)
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