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參數(shù)資料
| 型號： | ML9041-01BCVWA |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175 |
| 封裝： | 10.62 X 2.55 MM, GOLD BUMP, DIE-175 |
| 文件頁數(shù)： | 32/57頁 |
| 文件大?。?/td> | 542K |
| 代理商： | ML9041-01BCVWA |
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PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
38/60
10) Busy Flag/Address Counter Read (Execution time: 1
s)
RS1
1
RS0
0
R/
W
1
DB7
BF
DB6
O6
DB5
O5
DB4
O4
DB3
O3
DB2
O2
DB1
O1
DB0
O0
Instruction code:
The “BF” bit (DB7) of this instruction tells whether the ML9041 is busy in internal operation (BF = “1”) or not
(BF = “0”).
When the “BF” bit is “1”, the ML9041 cannot accept any other instructions. Before inputting a new instruction,
check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9041 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
RS1
1
RS0
1
R/
W
1
DB7
P7
DB6
P6
DB5
P5
DB4
P4
DB3
P3
DB2
P2
DB1
P1
DB0
P0
Instruction code:
A character code (P
7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a
character pattern (P
7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Transfer Mode
Setting instruction (see 3).
Note: Conditions for reading correct data
(1)
The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2)
When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3)
When two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note:
The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
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PDF描述 |
|---|---|
| ML9041A-XXACVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189 |
| ML9042-XXCVWA | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
| ML9044-XXACVWA | 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189 |
| ML9044-51ACVWA | 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189 |
| ML9044A-51ACVWA | 17 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML9041A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER DRIVER |
| ML9041A-XXACVWA | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER DRIVER |
| ML9041A-XXBCVWA | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER DRIVER |
| ML9042 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:DOT MATRIX LCD CONTROLLER DRIVER |
| ML9042-54CVWA-5016 | 制造商:ROHM Semiconductor 功能描述:RHOML9042-54CVWA-5016 OKI LCD DRIVER |
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