參數(shù)資料
型號(hào): ML9040A-BXXWA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 顯示控制器
英文描述: 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC81
封裝: ALUMINUM PAD, DIE-81
文件頁(yè)數(shù): 27/50頁(yè)
文件大?。?/td> 465K
代理商: ML9040A-BXXWA
ML9040A-Axx/-Bxx
Semiconductor
32/49
PEDL9040A-03
H
R/W
Instruction code
L
RS
BF
DB7
O6
DB6
O5
DB5
O4
DB4
O3
DB3
O2
DB2
O1
DB1
O0
DB0
H
R/W
Instruction code
H
RS
P7
DB7
P6
DB6
P5
DB5
P4
DB4
P3
DB3
P2
DB2
P1
DB1
P0
DB0
(10) Busy flag and address counter read (Execution time is 1 ms.)
The busy flag (BF) is output by this instruction to indicate whether the ML9040A-Axx/
-Bxx is engaged in internal operations (BF = "H") or not (BF = "L").
When BF = "H", no new instruction is accepted. It is therefore necessary to verify BF =
"L" before inputting a new instruction.
When BF = "L", a correct address counter value is output. The address counter value
must match the DD RAM address or CG RAM address. The decision of whether it is
a DD RAM address or CG RAM address is made by the address previously set.
Since the address counter value when BF = "H" is sometimes incremented or decremented
by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
Character codes (bits P7 to P0) are read from the DD RAM, while character patterns (P7
to P0) from the CG RAM.
Selection of DD RAM or CG RAM is decided by the address previously set.
After reading those data, the address counter (ADC) is incremented or decremented by
1 as set by the shift mode mentioned in item "(3) shift mode set".
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(Note) Conditions for the reading of correct data:
1 When the DD RAM address set or CG RAM address set is input before
inputting this instruction.
2 When the cursor/display shift is input before inputting this instruction in
case the character code is read.
3 Data after the second reading from RAM when read more than 2 times.
Correct data is not output in any other case.
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