
FEDL87V3104-02
OKI Semiconductor
ML87V3104
5/69
FUNCTIONAL DESCRIPTION
1. Display Memory
The address and data configuration of the display memory is specified by making control register settings.
When the set memory size is smaller than the internal DRAM (4M bits), the page mode operation is started
automatically, making it possible to specify the display address in units of a page and to access the host CPU (a
maximum of 256 pages). Even when the address space of the host CPU bus is smaller than the display memory
space, the entire area can be accessed using the page mode.
There are limitations on the LCD drive mode depending on the display memory data width. (See Section 3.1.)
Control registers:
IMASZX [#03h: bit 3-0]: Display memory horizontal size (2
n) (Table F1.1)
IMASZY [#03h: bit 7-4]: Display memory vertical size (2
n)
(Table F1.1)
IMDBPP [#02h: bit 1-0]: Number of bits per pixel
(Table F1.2)
HSTPGA [#3Bh]:
Page number for host access
Table F1.1 Display memory size selection
IMASZY
Vertical size
(lines)
IMASZX
Horizontal size
(pixels)
0 0 0 0
64
0 0 0 0
64
0 0 0 1
128
0 0 0 1
128
0 0 1 0
256
0 0 1 0
256
0 0 1 1
512
0 0 1 1
512
0 1 0 0
1024
0 1 0 0
1024
0 1 0 1
2048
0 1 0 1
2048
0 1 1 0
4096
0 1 1 0
4096
0 1 1 1
(Reserved)
0 1 1 1
(Reserved)
1 X X X
(Reserved)
1 X X X
(Reserved)
Table F1.2 Display memory data width
Number of simultaneously displayed colors
IMDBPP
Number of bits
(bits/pixel)
Color mode
Monochrome mode
Applicable LCD type
0
X
—
0
1
0
4
16/4096
16
0
1
8
Using color
palette
256/4096
256
STN/TFT
4096/4096
—
STN
1
0
16*
1
Direct color
65536/65536
—
TFT
*1: Correspondence between the display memory data and the color data in the 16 BPP mode.
Upper byte
Lower byte
R
0
R
3
R
2
R
1
B
0
B
3
B
2
B
1
G
3
G
2
G
1
G
0
70
0
7
Upper byte
Lower byte
R
5
R
4
R
3
R
2
R
1
B
5
B
4
B
3
B
2
B
1
G
5
G
4
G
3
G
2
G
1
G
0
70
0
7
STN 16 BPP
TFT 16 BPP
(12)
(no use)