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參數(shù)資料
| 型號： | ML67Q5002TC |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 233K |
| 代理商： | ML67Q5002TC |
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
13/24
Pin Name
I/O
Description
Primary
/
Secondary
Logic
I2C
SDA
I/O
I2C Data. This pin operates as NMOS Open drain. Connect pull-up
resistor.
Secondary
Positive
SCL
O
I2C Clock. This pin operates as NMOS Open drain. Connect pull-up
resistor.
Secondary
—
Synchronous SIO
SCLK
I/O
Serial clock
Secondary
—
SDI
I
Serial receive data
Secondary
Positive
SDO
O
Serial transmit data
Secondary
Positive
PWM signals
PWMOUT[0]
O
PWM output of CH0
Secondary
Positive
PWMOUT[1]
O
PWM output of CH1
Secondary
Positive
Analog-to-digital converter
AIN[0]
I
Ch0 analog input
—
AIN[1]
I
Ch1 analog input
—
AIN[2]
I
Ch2 analog input
—
AIN[3]
I
Ch3 analog input
—
VREFP
I
Analog-to-digital converter convert reference voltage
—
VREFN
I
Analog-to-digital converter convert reference GND
—
AVDD
Analog-to-digital converter power supply
—
AGND
Analog-to-digital converter ground
—
Interrupt signals
EXINT[3:0]
I
External interrupt input signals
Secondary
Positive
/
Negative
EFIQ_N
I
External fast interrupt input signal.
Interrupt controller connects this to CPU FIQ input.
Secondary
Negative
MODE configuration
DRAME_N
I
DRAM enable mode
—
Negative
TEST
I
Test mode
—
Positive
TEST1
I
Test mode
—
Positive
FWR
I
Test mode
—
Positive
JSEL
I
JTAG select signal. L: On-board debug, H: Boundary scan.
—
Power supplies
VDD_CORE
Core power supply
—
VDD_IO
I/O power supply
—
GND
GND for core and I/O
—
PLLVDD
PLL power supply
—
PLLGND
GND for PLL
—
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