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參數(shù)資料
| 型號： | ML67Q5002LA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 233K |
| 代理商： | ML67Q5002LA |
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
11/24
Pin Name
I/O
Description
Primary /
Secondary
Logic
External Bus
XA[23:19]
O
Address bus to external RAM, external ROM, external I/O banks, and
external DRAM. After a reset, these pins are configured for their primary
function (PIOC[6:2]).
Secondary
Positive
XA[18:0]
O
Address bus to external RAM, external ROM, external I/O banks, and
external DRAM.
—
Positive
XD[15:0]
I/O
Data bus to external RAM, external ROM, external I/O banks, and external
DRAM.
—
Positive
External bus control signals (ROM/SRAM/IO)
XROMCS_N
O
ROM bank chip select
—
Negative
XRAMCS_N
O
SRAM bank chip select
—
Negative
XIOCS_N[0]
O
IO chip select 0
—
Negative
XIOCS_N[1]
O
IO chip select 1
—
Negative
XIOCS_N[2]
O
IO chip select 2
—
Negative
XIOCS_N[3]
O
IO chip select 3
—
Negative
XOE_N
O
Output enable/ Read enable
—
Negative
XWE_N
O
Write enable
—
Negative
XBS_N[1:0]
O
Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB
—
Negative
XBWE_N[0]
O
LSB Write enable
—
Negative
XBWE_N[1]
O
MSB Write enable
—
Negative
XWR
O
Data transfer direction for external bus, used when connecting to Motorola
I/O devices. This represent the secondary function of pin PIOC[7].
L: read , H: write. Available for I/O bank 0/1.
Secondary
—
XWAIT
I
External I/O bank 0/1/2/3 WAIT signal.
This input permits access to devices slower than register settings.
Secondary
Positive
External bus control signals (DRAM)
XRAS_N
O
Row address strobe. Used for both EDO DRAM and SDRAM
Secondary
Negative
XCAS_N
O
Column address strobe signal (SDRAM)
Secondary
Negative
XSDCLK
O
SDRAM clock (same frequency as internal HCLK)
Secondary
—
XSDCKE
O
Clock enable (SDRAM)
Secondary
—
XSDCS_N
O
Chip select (SDRAM)
Secondary
Negative
XDQM[1]/XCAS_N[1]
O
Connected to SDRAM: DQM (MSB)
Connected to EDO DRAM: column address strobe signal (MSB)
Secondary
Positive/
Negative
XDQM[0]/XCAS_N[0]
O
Connected to SDRAM: DQM (LSB)
Connected to EDO DRAM: column address strobe signal (LSB)
Secondary
Positive/
Negative
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