參數(shù)資料
型號(hào)： ML67Q5002LA
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144
封裝： 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 650K
代理商： ML67Q5002LA
ML675001/ML67Q5002/ML67Q5003
14 Oki Semiconductor
April 2004, Rev 2.0
RI
O
Ring Indicator.
Indicates that the modem or data set has received a telephone ring indicator. Bit 6 in the
modem status register reects this input.
Secondary
Negative
SIO Interface
STXD
O
SIO transmit signal.
Secondary
Positive
SRXD
I
SIO receive signal.
Secondary
Positive
I2C Interface
SDA
I/O
I2C Data. This pin operates as NMOS Open drain. Connect pull-up resistor.
Secondary
—
SCL
O
I2C Clock. This pin operates as NMOS Open drain. Connect pull-up resistor.
Secondary
—
Synchronous SIO Interface
SCLK
I/O
Serial clock.
Secondary
—
SDI
I
Serial receive data.
Secondary
—
SDO
O
Serial transmit data.
Secondary
—
Pulse Width Modulator (PWM) Interface
PWMOUT[0]
O
PWM output of Ch 0.
Secondary
Positive
PWMOUT[1]
O
PWM output of Ch 1.
Secondary
Positive
Analog-to-digital Converter Interface
AIN[0]
I
Ch 0 analog input
—
AIN[1]
I
Ch 1 analog input
—
AIN[2]
I
Ch 2 analog input
—
AIN[3]
I
Ch 3 analog input
—
VREFP
I
Analog-to-digital converter reference voltage
—
VREFN
O
Analog-to-digital converter reference voltage return to ground
—
Interrupt Interface
EXINT[3:0]
I
Interrupt input signals
Secondary
Positive / Negative
EFIQ_N
I
Negative-edge-triggered interrupt input signal. Interrupt controller connects this to CPU FIQ
input
Secondary
Negative
MODE Configuration Interface
DRAME_N
I
DRAM enable mode
—
Negative
TEST
I
Test mode
—Positive
TEST1
I
Test mode
—Positive
FWR
I
Test mode
—Positive
JSEL
I
JTAG select signal: L = On-board debug, H = Boundary scan
—
Power and Ground Interface
AVDD
Analog-to-digital converter power supply, 3.3 V
—
AGND
Analog-to-digital converter ground
—
VDD_CORE
Core power supply, 2.5 V
—
VDD_IO
I/O power supply, 3.3 V
—
GND
GND for core and I/O
—
PLLVDD
PLL power supply, 2.5 V
PLLGND
GND for PLL
Pin Descriptions (Continued)
Pin Name
I/O
Description
Primary/
Secondary
Logic
相關(guān)PDF資料
PDF描述
ML675001LA 32-BIT, 60 MHz, RISC MICROCONTROLLER, PBGA144
ML67Q5003TC 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
ML675001TC 32-BIT, 60 MHz, RISC MICROCONTROLLER, PQFP144
ML67Q5002TC 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
ML67Q5002LA 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144
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