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參數(shù)資料
| 型號： | ML675001LA |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 60 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 650K |
| 代理商： | ML675001LA |
ML675001/ML67Q5002/ML67Q5003
16 Oki Semiconductor
April 2004, Rev 2.0
Input leakage current [3]
IIH/IIL
[4]
VI = 0 V to VDD_IO
-50
—
50
A
IIL
[5]
VI = 0 V, Pull-up resistance of 50 kohm
-200
-73
-10
II
[6]
VI = 0V to AVDD
-5
—
5
Output leak current, 3-state output in High-
impedance mode[3]
ILO
VO = 0 V to VDD_IO
-50
—
50
A
Input pin capacitance
CI
——
6
—
pF
Output pin capacitance
CO
——
9
—
pF
I/O pin capacitance
CIO
——
10
—pF
Analog reference power supply current
IREF
Analog-to-digital converter enabled [7]
—
320
650
A
Analog-to-digital converter disabled
—
1
2
Power Supply Current (STANDBY)
IDDS_CORE
TA = 25°C
[8]
—20
150
A
IDDS_IO
—10
40
Power Supply Current (HALT) [9]
IDDH_CORE
fOP = 60 MHz
CL = 30 pF
37
55
mA
IDDH_IO
—6
10
Power Supply Current (RUN) [10]
IDD_CORE
—75
120
mA
IDD_IO
—17
25
1.
All output pins except XA[15:0].
2.
XA[15:0].
3.
The absolute value of leakage current into the device is shown as (+) and current out of the device is shown as (-).
4.
All input pins except RESET_N.
5.
RESET_N pin, with 50 k
pull-up resistance.
6.
Analog input pins (AIN0 to AIN3).
7.
Analog-Digital Converter operation ratio is 20%.
8.
VDD_IO or 0 V for input ports; no load for other pins.
9.
DRAM function stopped by deasserting the DRAME_N pin.
10. Cacheable setting and external ROM used.
Analog-to-Digital Converter Characteristics [1]
(VDD_CORE = 2.5 V, VDD_IO = 3.3 V, AVDD = 3.3 V, TA = 25°C)
Item
Symbol
Conditions
Minimum
Typical
Maximum
Unit
Resolution [2]
n—
—
10
bit
Linearity error [3]
EL
Analog input source impedance Ri
≤ 1k
—±3
—
lsb
Differential linearity error [4]
ED
—±3
—
Zero scale error [5]
EZS
—±3
—
Full scale error [6]
EFS
—±3
—
Conversion time
tCONV
—5
—
s
Throughput
—
10
—
200
kHz
1.
VDD_IO and AVDD should be supplied separately.
2.
Resolution: Minimum input analog value recognized. For 10-bit resolution, this is (VREF – AGND) ÷1024.
3.
Linearity error: Difference between the theoretical and actual conversion characteristics. (Note that it does not include quantization error.) The theoretical conversion characteristic divides the voltage range between VREF and AGND
into 1024 equal steps.
4.
Differential linearity error: Difference between the theoretical and actual input voltage change producing a 1-bit change in the digital output anywhere within the conversion range. This is an indicator of conversion characteristic
smoothness. The theoretical value is (VREF – AGND) ÷ 1024.
5.
Zero scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from “0x000” to “0x001.”
6.
Full scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from “0x3FE” to “0x3FF.”
DC Characteristics
(VDD_CORE = 2.25 to 2.75 V, VDD_IO = 3.0 to 3.6 V, TA = -40 to +85°C) (Continued)
Item
Symbol
Conditions
Minimum
Typical
Maximum
Unit
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