![](http://datasheet.mmic.net.cn/120000/ML66525-XXTB_datasheet_3559839/ML66525-XXTB_457.png)
Chapter 16
Appendix
Instruction Set
XVI - 9
MOVB
(Am),Dn
MOVB
(d8,Am),Dn
MOVB
(d16,Am),Dn
MOVB
(d32,Am),Dn
MOVB
(d8,SP),Dn
MOVB
(d16,SP),Dn
MOVB
(d32,SP),Dn
MOVB
(Di,Am),Dn
MOVB
(abs16),Dn
MOVB
(abs32),Dn
MOVB
Dm,(An)
MOVB
Dm,(d8,An)
MOVB
Dm,(d16,An)
MOVB
Dm,(d32,An)
MOVB
Dm,(d8,SP)
MOVB
Dm,(d16,SP)
MOVB
Dm,(d32,SP)
MOVB
Dm,(Di,An)
MOVB
Dm,(abs16)
MOVB
Dm,(abs32)
MOVHU
(Am),Dn
MOVHU
(d8,Am),Dn
MOVHU
(d16,Am),Dn
MOVHU
(d32,Am),Dn
MOVHU
(d8,SP),Dn
MOVHU
(d16,SP),Dn
MOVHU
(d32,SP),Dn
MOVHU
(Di,Am),Dn
MOVHU
(abs16),Dn
MOVHU
(abs32),Dn
MOVHU
Dm,(An)
MOVHU
Dm,(d8,An)
MOVHU
Dm,(d16,An)
MOVHU
Dm,(d32,An)
MOVHU
Dm,(d8,SP)
MOVHU
Dm,(d16,SP)
MOVHU
Dm,(d32,SP)
MOVHU
Dm,(Di,An)
MOVHU
Dm,(abs16)
MOVHU
Dm,(abs32)
mem8(Am)(sign_ext)
→
Dn
mem8(d8(sign_ext)+Am)(sign_ext)
→
Dn
mem8(d16(sign_ext)+Am)(sign_ext)
→
Dn
mem8(d32+Am)(sign_ext)
→
Dn
mem8(d8(zero_ext)+SP)(sign_ext)
→
Dn
mem8(d16(zero_ext)+SP)(sign_ext)
→
Dn
mem8(d32+SP)(sign_ext)
→
Dn
mem8(Di+Am)(sign_ext)
→
Dn
mem8(abs16(zero_ext))(sign_ext)
→
Dn
mem8(abs32)(sign_ext)
→
Dn
Dm
→
mem8(An)
Dm
→
mem8(d8(sign_ext)+An)
Dm
→
mem8(d16(sign_ext)+An)
Dm
→
mem8(d32+An)
Dm
→
mem8(d8(zero_ext)+SP)
Dm
→
mem8(d16(zero_ext)+SP)
Dm
→
mem8(d32+SP)
Dm
→
mem8(Di+An)
Dm
→
mem8(abs16(zero_ext))
Dm
→
mem8(abs32)
mem16(Am)(zero_ext)
→
Dn
mem16(d8(sign_ext)+Am)(zero_ext)
→
Dn
mem16(d16(sign_ext)+Am)(zero_ext)
→
Dn
mem16(d32+Am)(zero_ext)
→
Dn
mem16(d8(zero_ext)+SP)(zero_ext)
→
Dn
mem16(d16(zero_ext)+SP)(zero_ext)
→
Dn
mem16(d32+SP)(zero_ext)
→
Dn
mem16(Di+Am)(zero_ext)
→
Dn
mem16(abs16(zero_ext))(zero_ext)
→
Dn
mem16(abs32)(zero_ext)
→
Dn
Dm
→
mem16(An)
Dm
→
mem16(d8(sign_ext)+An)
Dm
→
mem16(d16(sign_ext)+An)
Dm
→
mem16(d32+An)
Dm
→
mem16(d8(zero_ext)+SP)
Dm
→
mem16(d16(zero_ext)+SP)
Dm
→
mem16(d32+SP)
Dm
→
mem16(Di+An)
Dm
→
mem16(abs16(zero_ext))
Dm
→
mem16(abs32)
-
3
4
5
7
4
5
7
3
4
7
2
3
4
6
3
4
6
2
3
6
2
3
4
6
3
4
6
2
3
6
2
3
4
6
3
4
6
2
3
6
2
3
2
3
2
3
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
D0
D1
D2
D4
D1
D2
D4
D0
S2
D4
D0
D1
D2
D4
D1
D2
D4
D0
S2
D4
1
1111
001
1
1111
0000
1111
2
0000
1000
1010
11
0
1000
1010
11
0
0100
10Dn
11
0
0000
1000
1010
11
0
1000
1010
11
0
0100
Dm1
1
11
0
3
01
10
01
10
01
10
01
10
101
1
101
1
101
1
10Dn
<abs16
1010
0
111
0
111
0
111
0
111
1001
11
D
m
<abs16
1000
4
DnAm
11
D
n
11
D
n
11
D
n
DiAm
....
11
D
n
DmAn
Dm1
1
Dm1
1
Dm1
1
DiAn
....
Dm1
1
5
<d8
<d16
<d32
<d8
<d16
<d32
....
<abs32
<d8
<d16
<d32
<d8
<d16
<d32
....
<abs32
6
....>
....
....>
....
....>
....
....>
....
....>
....
....>
....
Group
Mnemonic
Operation
Machine
Code
Notes
Flag
Code
Size
Cycle
For
-mat
MN1030/MN103S
SERIES
INSTRUCTION
SET
7
....
8
....>
....
....>
....
....>
....
....>
....
9
....
10
....
11
....
12
....>
13
14
VF
CF
NF
ZF
MOVB
MOVHU