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參數(shù)資料
| 型號： | ML6510CQ-80 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ML6510CQ-80 |
March 1997
ML6510
Series Programmable Adaptive
Clock Manager (PACMan)
System block diagram
GENERAL DESCRIPTION
The ML6510 (Super PACMan) is a Programmable
Adaptive Clock Manager which offers an ideal solution
for managing high speed synchronous clock distribution in
next generation, high speed personal computer and
workstation system designs. It provides eight channels of
deskew buffers that adaptively compensate for clock
skew using only a single trace. The input clock can be
either TTL or PECL, selected by a bit in the control
register. Frequency multiplication or division is possible
using the M&N divider ratio, within the maximum
frequency limit. 0.5X, 1X, 2X and 4X clocks can be easily
realized.
The ML6510 is implemented using a low jitter PLL with
on-chip loop filter. The ML6510 deskew buffers adaptively
compensate for clock skew on PC boards. An internal
skew sense circuit is used to sense the skew caused by
the PCB trace and load delays. The sensing is done by
detecting a reflection from the load and the skew is
corrected adaptively via a unique phase control delay
circuit to provide low load-to-load skew, at the end of the
PCB traces. Additionally, the ML6510 supports PECL
reference clock outputs for use in the generation of clock
trees with minimal part-to-part skew. The chip configuration
can be programmed to generate the desired output
frequency using the internal ROM or an external serial
EEPROM or a standard two-wire serial microprocessor
interface.
FEATURES
s
Input clocks can be either TTL or PECL with low
input to output clock phase error
s
8 independent, automatically deskewed clock
outputs with up to 5ns of on-board deskew range
(10ns round trip)
s
Controlled edge rate TTL-compatible CMOS clock
outputs capable of driving 40 PCB traces
s
10 to 80MHz (6510-80) or 10 to 130MHz (6510-130)
input and output clock frequency range
s
Less than 500ps skew between inputs at the
device loads
s
Small-swing reference clock outputs for minimizing
part-to-part skew
s
Frequency multiplication or division is possible using
the M&N divider ratio
s
Lock output indicates PLL and deskew buffer lock
s
Test mode operation allows PLL and deskew buffer
bypass for board debug
s
Supports industry standard processors like Pentium,
Mips, SPARC, PowerPC, Alpha, etc.
CPU
CACHE
RAM
LOCAL BUS
MEMORY BUS
CACHE
CONTROLLER
MEMORY BUS
CONTROLLER
ML6510
CLK
CLOCK OUT TO
COMPONENTS
8
CLOCK SUBSYSTEM
CLOCK IN
REV. 1.0 10/25/2000
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