參數(shù)資料
型號(hào): ML6426-3
廠商: Fairchild Semiconductor Corporation
英文描述: High Bandwidth Triple Video Filters with Buffered Outputs for RGB or YUV
中文描述: 高帶寬三路視頻濾波器與緩沖為RGB或YUV輸出
文件頁數(shù): 2/17頁
文件大小: 287K
代理商: ML6426-3
ML6426
2
November, 1999
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
A/
B
MUX
Logic input pin to select between
Bank <A> and Bank <B> video inputs.
This pin is internally pulled high.
2
R
IN
A/Y
IN
A
Unfiltered analog R- or Y-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
3
GND
Analog ground
4
V
CC
Analog 5V supply
5
R
IN
B/Y
IN
B
Unfiltered analog R- or Y-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
6
G
IN
A/U
IN
A Unfiltered analog G- or U-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
7
G
IN
B/U
IN
B
Unfiltered analog G- or U-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
PIN
NAME
FUNCTION
8
B
IN
A/V
IN
A
Unfiltered analog B- or V-channel
input for Bank <A>. Sync must be
provided at SYNC IN pin.
9
B
IN
B/V
IN
B
Unfiltered analog B- or V-channel
input for Bank <B>. Sync must be
provided at SYNC IN pin.
10
B
OUT
Analog B or V-channel output
11
G
OUT
Analog G or U-channel output
12
V
CCO
5V power supply for output buffers
13
R
OUT
Analog R or Y-channel output
14
GNDO
Analog ground
15
DISABLE
Disable/Enable pin. Turns the chip off
when logic high. Internally pulled low.
16
SYNC IN
Input for an external H-sync logic
signal for filter channels. CMOS
level input. Active High.
ML6426
16-Pin Narrow SOIC (S16N)
1
A/
B
MUX
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
RINA/YINA
GND
VCC
RINB/YINB
GINA/UINA
GINB/UINB
BINA/VINA
SYNC IN
DISABLE
GNDO
ROUT/YOUT
VCCO
GOUT/UOUT
BOUT/VOUT
BINB/VINB
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ML6426-4 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:High Bandwidth Triple Video Filters with Buffered Outputs for RGB or YUV
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ML6426CS15 功能描述:有源濾波器 Tripple Video Filter Hi Bandwidth RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube