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參數(shù)資料
| 型號： | ML6401CS-3 |
| 英文描述： | 8-Bit 20 MSPS A/D Converter |
| 中文描述： | 8位20 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 554K |
| 代理商： | ML6401CS-3 |
2
ML6401
PIN CONFIGURATION
ML6401-1
24-Pin SOIC (S24W)
ML6401-3
16-Pin SOIC (S16N)
GND
D
V
IN
–
V
IN–BIAS
GNDA
GNDA
V
IN
+
VDD
A
VREF
IN
VREF
OUT
VDD
A
VDD
A
VDD
D
OE
GND
O
D0
D1
D2
D3
D4
D5
D6
D7
VDD
O
CLK
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
OE
GND
D
GND
A
V
IN
+
VDD
A
VDD
D
CLK
VDD
D
D0
D1
D2
D3
D4
D5
D6
D7
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
TOP VIEW
PIN
1
NAME
OE
DESCRIPTION
Output Enable. A logic low signal
on this pin enables the outputs.
(16)
2
GND
O
Output ground pin.
3
(1)
D0
D0 (LSB) output signal (TTL
compatible).
4
(2)
D1
D1 output signal (TTL compatible).
5
(3)
D2
D2 output signal (TTL compatible).
6
(4)
D3
D3 output signal (TTL compatible).
7
(5)
D4
D4 output signal (TTL compatible).
8
(6)
D5
D5 output signal (TTL compatible).
9
(7)
D6
D6 output signal (TTL compatible).
10 (8)
D7
D7 (MSB) output signal (TTL
compatible).
11
VDD
O
Output supply pin.
12 (10)
CLK
Clock input pin.
PIN
13 (9,11) VDD
D
NAME
DESCRIPTION
Digital supply pin.
14 (12)
VDD
A
Analog supply pin.
15 (12)
VDD
A
Analog supply pin.
16
VREF
OUT
Full scale reference output.
Connect to pin 17 for self bias.
(VRTS on 1175) (ML401-1 only)
17
VREF
IN
Full scale reference input.
Connect to pin 16 for self bias.
(VRT on 1175) (ML401-1 only)
18 (12)
VDD
A
Analog supply pin.
19 (13)
V
IN
+
Input signal.
20 (14)
GND
A
Analog ground.
21 (14)
GND
A
Analog ground.
22
V
IN–BIAS
Common mode bias output.
Connect to pin 23 for self bias.
(VRBS on 1175) (ML401-1 only)
23
V
IN
–
Common mode bias input.
Connect to pin 22 for self bias.
Drive with the negative input if
differential input is being used.
(VRB on 1175)
(ML401-1 only)
24 (15)
GND
D
Digital Ground.
PIN DESCRIPTION
(Pin numbers in parentheses are for S16N package)
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