參數(shù)資料
型號(hào): ML610Q482P-XXXWA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4.2 MHz, RISC MICROCONTROLLER, UUC48
封裝: CHIP-48
文件頁(yè)數(shù): 15/27頁(yè)
文件大小: 353K
代理商: ML610Q482P-XXXWA
FEDL610Q482P-01
OKI SEMICONDUCTOR
ML610Q482P
22/27
AC CHARACTERISTICS (Synchronous Serial Port)
(VDD = 1.3 to 3.6V, VSS = 0V, Ta = 40 to +85°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
When RC oscillation is active *
2
(VDD = 1.3 to 3.6V)
10
μs
SCLK input cycle
(slave mode)
tSCYC
When high-speed oscillation is
active *
3(VDD = 1.8 to 3.6V)
1
μs
SCLK output cycle
(master mode)
tSCYC
SCLK*
1
s
When RC oscillation is active *
2
(VDD = 1.3 to 3.6V)
4
μs
SCLK input pulse width
(slave mode)
tSW
When high-speed oscillation is
active *
3(VDD = 1.8 to 3.6V)
0.4
μs
SCLK output pulse width
(master mode)
tSW
SCLK*
1
×0.4
SCLK*
1
×0.5
SCLK*
1
×0.6
s
When RC oscillation is active *
2
(VDD = 1.3 to 3.6V)
500
SOUT output delay time
(slave mode)
tSD
When high-speed oscillation is
active *
3(VDD = 1.8 to 3.6V)
240
ns
When RC oscillation is active *
2
(VDD = 1.3 to 3.6V)
500
SOUT output delay time
(master mode)
tSD
When high-speed oscillation is
active *
3(VDD = 1.8 to 3.6V)
240
ns
SIN input setup time
(slave mode)
tSS
80
ns
When RC oscillation is active *
2
(VDD = 1.3 to 3.6V)
500
SIN input setup time
(master mode)
tSS
When high-speed oscillation is
active *
3(VDD = 1.8 to 3.6V)
240
ns
When RC oscillation is active *
2
(VDD = 1.3 to 3.6V)
300
SIN input hold time
tSH
When high-speed oscillation is
active *
3(VDD = 1.8 to 3.6V)
80
ns
*
1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
*
2: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)
*
3: When Crystal/ceramic oscillation , built-in PLL oscillation , or external clock input is selected with OSCM1–0 of the
frequency control register (FCON0)
tSD
SCLK0*
SIN0*
SOUT0*
*: Indicates the secondary function of the port.
tSD
tSS
tSH
tSW
tSCYC
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