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| 型號： | ML610Q408-NNNWA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, UUC88 |
| 封裝： | 2.27 X 2.23 MM, 0.35MM HEIGHT, 0.80 MM PITCH,DIE-88 |
| 文件頁數(shù)： | 56/62頁 |
| 文件大?。?/td> | 1994K |
| 代理商： | ML610Q408-NNNWA |
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ML610Q407/ML610Q408/ML610Q409 User’s Manual
Contents
Contents –1
Chapter 4
4. MCU Control Function......................................................................................................................................................... 4-1
4.1 Overview ...................................................................................................................................................................... 4-1
4.1.1
Features................................................................................................................................................................. 4-1
4.1.2
Configuration........................................................................................................................................................ 4-1
4.2 Description of Registers ............................................................................................................................................... 4-2
4.2.1
List of Registers .................................................................................................................................................... 4-2
4.2.2
Stop Code Acceptor (STPACP) ............................................................................................................................ 4-3
4.2.3
Standby Control Register (SBYCON) .................................................................................................................. 4-4
4.2.4
Block Control Register 0 (BLKCON0) ................................................................................................................ 4-5
4.2.5
Block Control Register 1 (BLKCON1) ................................................................................................................ 4-6
4.2.6
Block Control Register 2 (BLKCON2) ................................................................................................................ 4-7
4.2.7
Block Control Register 3 (BLKCON3) ................................................................................................................ 4-8
4.2.8
Block Control Register 4 (BLKCON4) ................................................................................................................ 4-9
4.3 Description of Operation ............................................................................................................................................ 4-10
4.3.1
Program Run Mode............................................................................................................................................. 4-10
4.3.2
HALT Mode........................................................................................................................................................ 4-10
4.3.3
STOP mode......................................................................................................................................................... 4-11
4.3.3.1
STOP Mode When CPU Operates with Low-Speed Clock ................................................................................................. 4-11
4.3.3.2
STOP Mode When CPU Operates with High-Speed Clock................................................................................................. 4-12
4.3.4
Note on Return Operation from STOP/HALT Mode.......................................................................................... 4-13
4.3.5
Block Control Function ...................................................................................................................................... 4-14
Chapter 5
5. Interrupts............................................................................................................................................................................... 5-1
5.1 Overview ...................................................................................................................................................................... 5-1
5.1.1
Features................................................................................................................................................................. 5-1
5.2 Description of Registers ............................................................................................................................................... 5-2
5.2.1
List of Registers .................................................................................................................................................... 5-2
5.2.2
Interrupt Enable Register 1 (IE1).......................................................................................................................... 5-3
5.2.3
Interrupt Enable Register 2 (IE2).......................................................................................................................... 5-4
5.2.4
Interrupt Enable Register 3 (IE3).......................................................................................................................... 5-5
5.2.5
Interrupt Enable Register 4 (IE4).......................................................................................................................... 5-6
5.2.6
Interrupt Enable Register 5 (IE5).......................................................................................................................... 5-7
5.2.7
Interrupt Enable Register 6 (IE6).......................................................................................................................... 5-8
5.2.8
Interrupt Enable Register 7 (IE7).......................................................................................................................... 5-9
5.2.9
Interrupt Request Register 0 (IRQ0)................................................................................................................... 5-10
5.2.10 Interrupt Request Register 1 (IRQ1)................................................................................................................... 5-11
5.2.11 Interrupt Request Register 2 (IRQ2)................................................................................................................... 5-13
5.2.12 Interrupt Request Register 3 (IRQ3)................................................................................................................... 5-14
5.2.13 Interrupt Request Register 4 (IRQ4)................................................................................................................... 5-15
5.2.14 Interrupt Request Register 5 (IRQ5)................................................................................................................... 5-16
5.2.15 Interrupt Request Register 6 (IRQ6)................................................................................................................... 5-17
5.2.16 Interrupt Request Register 7 (IRQ7)................................................................................................................... 5-18
5.3 Description of Operation ............................................................................................................................................ 5-19
5.3.1
Maskable Interrupt Processing............................................................................................................................ 5-20
5.3.2
Non-Maskable Interrupt Processing ................................................................................................................... 5-20
5.3.3
Software Interrupt Processing............................................................................................................................. 5-20
5.3.4
Notes on Interrupt Routine ................................................................................................................................. 5-21
5.3.5
Interrupt Disable State ........................................................................................................................................ 5-24
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML610Q408P-NNNWA | RISC MICROCONTROLLER, UUC88 |
| ML610Q407P-NNNTBZ03A | RISC MICROCONTROLLER, PQFP100 |
| ML610Q409P-NNNTBZ03A | RISC MICROCONTROLLER, PQFP100 |
| ML610Q409P-XXXTBZ03A | RISC MICROCONTROLLER, PQFP100 |
| ML610Q408-XXXWA | RISC MICROCONTROLLER, UUC88 |
相關(guān)代理商/技術(shù)參數(shù) |
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| ML610Q408P-NNNTB03A7 | 功能描述:MCU 8BIT 16K FLASH 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:Lapis 標(biāo)準(zhǔn)包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設(shè)備:電容感應(yīng)，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤 |
| ML610Q409 REFBOARD | 功能描述:BOARD REF ML610Q409/P RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Lapis 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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| ML610Q411 REFBOARD | 功能描述:BOARD REF ML610Q411/ML610Q411P RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Lapis 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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