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參數資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 55/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
58/81
EP3 Receive Byte Counter Register (EP3RXCNT)
Address
0 x 5B
Type
6-Bit data
Access type
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Receive byte count (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is
done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case
of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value
and reads out the data of one packet from the EP3 Receive FIFO.
This register will be invalid when the transfer direction of the EP is set for transmission.
The EP3RXCNT register is cleared under the following conditions.
1. When an OUT token is received for EP3.
2. When the local MCU resets the EP receive packet ready bit.
3. When the local MCU writes a “0” into the stall bit.
EP4, 5 Receive Byte LSB Counter Registers (EP4, 5RXCNTLSB)
Address
0 x 5C, 5D
Type
10-Bit or 9-bit data
Access type
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
Receive byte count LSB (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is
done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case
of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value
and reads out the data of one packet from the EP4/5 Receive FIFO. The lower 8 bits of the receive byte count are
stored in this register and the higher order bits are stored in the EP receive byte counter MSB.
This register will be invalid when the transfer direction of the EP is set for transmission.
The EP4,5RXCNT register is cleared under the following conditions.
1. When an OUT token is received for the EP.
2. When the local MCU resets the EP receive packet ready bit.
3. When the local MCU writes a “0” into the stall bit.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
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| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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