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參數(shù)資料
| 型號： | ML54053 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
| 封裝： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 235K |
| 代理商： | ML54053 |
Table of Contents
1. FEATURES ........................................................................................................... 2
2. BLOCK DIAGRAM ............................................................................................... 2
3. PIN SPECIFICATIONS ........................................................................................ 3
3.1 Host Interface ...................................................................................................... 3
3.2 NAND Flash Memory Interface .......................................................................... 4
3.3 Extended Bus Interface ...................................................................................... 5
3.4 Other Interfaces .................................................................................................. 5
3.5 Power Supply ....................................................................................................... 5
3.6 Pin Totals ............................................................................................................. 5
3.7 Pin Configuration ................................................................................................ 6
4. FUNCTIONS ........................................................................................................ 7
5. ATA REGISTERS ................................................................................................. 8
5.1 Memory Mapped Configuration ......................................................................... 8
5.2 I/O Mapped 16 Contiguous Registers Configuration ...................................... 9
5.3 Primary I/O Mapped Configuration ................................................................... 9
5.4 Secondary I/O Mapped Configuration ............................................................ 10
5.5 True IDE Mapped Configuration ...................................................................... 10
5.6 ATA Registers .................................................................................................... 11
5.6.1 Data Register (Write/Read) ...................................................................... 11
5.6.2 Error Register (Read Only) ....................................................................... 11
5.6.3 Feature Register (Write Only) ................................................................... 11
5.6.4 Sector Count Register (Write/Read) ........................................................ 11
5.6.5 Sector Number Register (Write/Read) ..................................................... 12
5.6.6 Cylinder Low Register (Write/Read) ......................................................... 12
5.6.7 Cylinder High Register (Write/Read) ........................................................ 12
5.6.8 Drive Head Register (Write/Read) ............................................................ 12
5.6.9 Status Register & Alternate Status Register (Read Only) ........................ 13
5.6.10 Device Control Register (Write Only) ....................................................... 13
5.6.11 Command Register (Write Only) .............................................................. 13
6. COMPACTFLASH INTERFACE ........................................................................ 14
6.1 ATA Commands (Standard) .............................................................................. 14
6.2 Commands for CompactFlash ......................................................................... 15
6.3 Vendor-Unique Commands .............................................................................. 15
6.4 Card Information Structure .............................................................................. 15
6.5 Identify Information ........................................................................................... 15
6.6 Number of Installed Memory Chips and CHS Structure ................................ 16
6.7 Modes ................................................................................................................. 17
6.7.1 Memory Mapped ..................................................................................... 17
6.7.2 I/O Mapped 16 Contiguous Registers ..................................................... 17
6.7.3 Primary I/O Mapped ................................................................................ 17
6.7.4 Secondary I/O Mapped ........................................................................... 17
6.7.5 True IDE ................................................................................................... 17
7. CHIP MODES .................................................................................................... 18
7.1 Types .................................................................................................................. 18
7.2 Settings .............................................................................................................. 18
7.3 Pin Assignment .................................................................................................. 18
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