參數(shù)資料
型號(hào)： ML54051
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PQFP120
封裝： 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120
文件頁(yè)數(shù)： 35/37頁(yè)
文件大?。?/td> 304K
代理商： ML54051
Semiconductor
ML54051
3/33
3. PIN SPECIFICATIONS
Refer to Section 12, “Application Examples” for specific connection examples.
3.1 Host Interface (PCMCIA)
Signal Name
ha [10:0]
hd [15:0]
hcen [2:1]
hiordn
hiowrn
hoen
hwen
hregn
hirqn
hstschgn
hinpackn
Type
I
B
I
O
Pin Count
11
16
2
1
Description
Address bus (A10 is MSB, A0 is LSB)
Data bus (D15 is MSB, D0 is LSB)
Card enable signal (hcen1 controls even addresses and hcen2 controls odd
addresses. The combination of ha0, hcen1 and hcen2 allows even/odd
addresses to be accessed by hd[7:0].)
I/O read signal (control signal to read data from ATA registers)
I/O write signal (control signal to write data to ATA registers)
Output enable signal
Write enable signal
Register select & I/O Enable signal
Interrupt request signal (when the card is configured as an I/O card)
Card status change signal (signal to change the status of the configuration
status register)
Input port acknowledge signal (acknowledge signal during I/O read)
hiois16n
O
1
16-bit address enable signal (when the card is configured as an I/O card,
this signal indicates that 16-bit addresses are enabled)
hwaitn
O
1
Wait signal
hspkr
B
1
Audio digital waveform signal
hrst
I
1
Reset signal
hcseln
I/(O)
1
Cable select signal (used only in True IDE Mode, GND: Master, X: Slave)
Total 42 pins
*
In an external CPU connection mode, hcseln functions as a control signal (xint) for the
extended bus.
I: Input, O: Output, B: Bidirectional
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