參數(shù)資料
型號(hào): ML4841CP
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Variable Feedforward PFC/PWM Controller Combo
中文描述: 0.5 A POWER FACTOR CONTROLLER WITH POST REGULATOR, PDIP16
封裝: PLASTIC, DIP-16
文件頁(yè)數(shù): 3/15頁(yè)
文件大小: 129K
代理商: ML4841CP
PRODUCT SPECIFICATION
ML4841
REV. 1.0.3 6/13/01
11
The ML4841 should be locally bypassed with a 10nF and a
1
F ceramic capacitor. In most applications, an electrolytic
capacitor of between 100
F and 330F is also required
across the part, both for ltering and as part of the start-up
bootstrap circuitry.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme.
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple volt-
age generated by the switching action. With such synchro-
nized switching, the ripple voltage of the rst stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
Figure 4. Typical Trailing Edge Control Scheme
RAMP
VEAO
TIME
VSW1
TIME
REF
EA
+
+
OSC
DFF
R
D
Q
CLK
U1
RAMP
CLK
U4
U3
C1
RL
I4
SW2
SW1
+
DC
I1
I2
I3
VIN
L1
U2
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