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參數(shù)資料
| 型號： | ML4824CS2 |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 103K |
| 描述： | IC PFC PWM CTRLR COMBO 16-SOIC |
| 標準包裝： | 45 |
| 模式： | 平均電流 |
| 頻率 - 開關： | 76kHz |
| 電流 - 啟動： | 700µA |
| 電源電壓： | 10.5 V ~ 13.2 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 管件 |
PRODUCT SPECIFICATION
ML4824
REV. 1.0.6 11/7/03
7
Functional Description
The ML4824 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWMs line regulation. In
either mode, the PWM stage uses conventional trailing-edge
duty cycle modulation, while the PFC uses leading-edge
modulation. This patented leading/trailing edge modulation
technique results in a higher useable PFC error amplier
bandwidth, and can signicantly reduce the size of the PFC
DC buss capacitor.
The synchronization of the PWM with the PFC simplies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the ML4824-1 runs at the same frequency as the
PFC. The PWM section of the ML4824-2 runs at twice the
frequency of the PFC, which allows the use of smaller PWM
output magnetics and lter capacitors while holding down
the losses in the PFC stage power components.
In addition to power factor correction, a number of protec-
tion features have been built into the ML4824. These include
soft-start, PFC over-voltage protection, peak current limit-
ing, brown-out protection, duty cycle limit, and under-
voltage lockout.
Power Factor Correction
Power factor correction makes a non-linear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with and proportional to the line
voltage, so the power factor is unity (one). A common class
of non-linear load is the input of most power supplies, which
use a bridge rectier and capacitive input lter fed from the
line. The peak-charging effect which occurs on the input
lter capacitor in these supplies causes brief high-amplitude
pulses of current to ow from the power line, rather than a
sinusoidal current in phase with the line voltage. Such
supplies present a power factor to the line of less than one
(i.e. they cause signicant current harmonics of the power
line frequency to appear at their input). If the input current
drawn by such a supply (or any other non-linear load) can be
made to follow the input voltage in instantaneous amplitude,
it will appear resistive to the AC line and a unity power factor
will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the ML4824 uses a boost-mode
DC-DC converter to accomplish this. The input to the
converter is the full wave rectied AC line voltage. No bulk
ltering is applied following the bridge rectier, so the
input voltage to the boost converter ranges (at twice line
frequency) from zero volts to the peak value of the AC input
and back to zero. By forcing the boost converter to meet two
simultaneous conditions, it is possible to ensure that the
current which the converter draws from the power line
agrees with the instantaneous line voltage. One of these
conditions is that the output voltage of the boost converter
must be set higher than the peak value of the line voltage.
A commonly used value is 385VDC, to allow for a high line
of 270VAC
rms
. The other condition is that the current which
the converter is allowed to draw from the line at any given
instant must be proportional to the line voltage. The rst of
these requirements is satised by establishing a suitable
voltage control loop for the converter, which in turn drives a
current error amplier and switching output driver. The
second requirement is met by using the rectied AC line
voltage to modulate the output of the voltage control loop.
Such modulation causes the current error amplier to
command a power stage current which varies directly with
the input voltage. In order to prevent ripple which will
necessarily appear at the output of the boost circuit (typically
about 10VAC on a 385V DC level) from introducing distor-
tion back through the voltage error amplier, the bandwidth
of the voltage loop is deliberately kept low. A nal rene-
ment is to adjust the overall gain of the PFC such to be
proportional to 1/V
IN
2
, which linearizes the transfer function
of the system as the AC input voltage varies.
Since the boost converter topology in the ML4824 PFC is of
the current-averaging type, no slope compensation is
required.
PFC Section
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
ML4824. The gain modulator is the heart of the PFC, as it is
this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line
voltage, and PFC output voltage. There are three inputs to
the gain modulator. These are:
1. A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectied AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at
I
AC
. Sampling current in this way minimizes ground
noise, as is required in high power switching power
conversion environments. The gain modulator responds
linearly to this current.
2. A voltage proportional to the long-term rms AC line
voltage, derived from the rectied line voltage after
scaling and ltering. This signal is presented to the gain
modulator at V
RMS
. The gain modulators output is
inversely proportional to V
RMS
2
(except at unusually
low values of V
RMS
where special gain contouring
takes over, to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between V
RMS
and gain is called K, and is
illustrated in the Typical Performance Characteristics.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ML4824CS-2 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Power Factor Correction and PWM Controller Combo |
| ML4824CS2_Q | 功能描述:功率因數(shù)校正 IC PFC Controller PWM Combo RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| ML4824CS2X | 功能描述:功率因數(shù)校正 IC PFC Controller PWM Combo RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| ML4824IP1 | 功能描述:功率因數(shù)校正 IC PFC Controller PWM Combo RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| ML4824IP-1 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Power Factor Correction and PWM Controller Combo |
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