參數(shù)資料
型號: ML4819CP
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Power Factor and PWM Controller “Combo”
中文描述: 1 A POWER FACTOR CONTROLLER WITH POST REGULATOR, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 7/15頁
文件大?。?/td> 269K
代理商: ML4819CP
ML4819
REV. 1.0 10/10/2000
7
SLOPE COMPENSATION
Slope compensation is accomplished by adding 1/2 of the
current flowing out of pin 12 to pin 1 (for the PFC section
and pin 9 (for the PWM section). The amount of slope
compensation is equal to (I
RAMP COMP
/2)
×
R
L
where R
L
is
the impedance to GND on pin 1 or pin 9. Since most of
the PWM applications will be limited to 50% duty cycle,
slope compensation should not be needed for the PWM
section. This can be defeated by using a low impedance
load to the current sense on pin 9.
500
400
300
200
100
0
0
100
200
300
400
500
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
1. 5V
SINE INPUT CURRENT (μA)
M
E
Figure 8. Gain Modulator Linearity
ENABLE
V
REF
V
REF
GEN.
9V
INTERNAL
BIAS
5V V
REF
V
CC
+
Figure 9. Under-Voltage Lockout Block Diagram
T
A
= 25 C
40
30
20
10
0
0
10
20
30
40
V
CC,
SUPPLY VOLTAGE (V)
I
C
Figure 10a. Total Supply Current vs. Supply Voltage
START-UP
25
30
35
20
15
10
5
00
10
20
30
40
50
60
70
TEMPERATURE ( C)
I
OPERATING
CURRENT
Figure 10b. Supply Current (I
CC
) vs. Temperature
OSC
10
20
12
R
T
R
SC
V
REF
I
R(SC)
TO PIN 9
TO PIN 1
I
R(SC)
2
I
R(SC)
2
9V
C
T
RAMP COMP
SLOPE
COMPENSATION
Q1
Figure 7. Slope Compensation Circuit
UNDER VOLTAGE LOCKOUT
On power-up the ML4819 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when V
CC
reaches 16V. When V
CC
drops
below 10V, the UVLO condition is imposed. During the
UVLO condition, the 5V V
REF
pin is “off”, making it
usable as a status flag.
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