參數(shù)資料
型號: ML4818
廠商: Fairchild Semiconductor Corporation
英文描述: Phase Modulation/Soft Switching Controller
中文描述: 相位調(diào)制/軟開關(guān)控制器
文件頁數(shù): 8/13頁
文件大?。?/td> 92K
代理商: ML4818
ML4818
PRODUCT SPECIFICATION
8
REV. 1.0.3 6/21/01
Figure 8. Output Drive Saturation Voltage vs.
Output Current
Figure 9. Output Rise/Fall Time
Output Driver Stage
The ML4818 has four high current high speed totem pole
output drivers each capable of 1.5A peak output, designed to
quickly switch the gates of capacitive loads, such as power
MOSFET transistors. Figure 8 illustrates the saturation char-
acteristics of the ouput drive transistors shown in Figure 7.
Typical rise and fall time characteristics of the output drivers
are illustrated with capacitive loads of 1nF and 10nF in
Figure 9.
Current Limit, Fault Detection and Soft Start
Current limit is implemented when the current sensed on I
LIM
reaches the 1V limit. At this point, the PWM cycle is termi-
nated. The flip flop (Figure 10) turns on the current source to
charge C
and remains on for the duration of the clock
period. When C
RST
has charged to 3.4V, a soft start reset
occurs. The number of times the PWM cycle is terminated
due to over-current is “remembered” on C
RST
. Over time,
C
RST
is discharged by R
RST
providing a measure of “forget-
ting” when the over-current condition no longer occurs. This
integrating fault detection is useful in differentiation between
short circuit and load surge conditions.
7
6
5
4
3
2
1
0
0
0.2
0.4
0.6
OUTPUT CURRENT (A)
0.8
1.0
1.2
1.4
S
SOURCE
SINK
~~
15
10
5
100
200
100
200
10nF
1nF
1nF
10nF
t
F
t
R
(ns)
O
Figure 10. Over-Current, Soft-Start, and Integrating Fault Detect Circuits
C
RST
+
R
RST
12
+
9
4
INHIBIT
OUTPUT
UNDER-VOLTAGE
LOCKOUT
CLOCK
3.4V
1.3V
RC
RESET
R
SENSE
R1
C1
V+
I2
S
Q
R
TERMINATE
PWM CYCLE
V+
I
1
SOFT START
I
SWITCH
C
SS
I
LIM
1V
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