參數(shù)資料
型號(hào): ML2259BCP
元件分類(lèi): 串行ADC
英文描述: レP Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer
中文描述: レP兼容的8位A / D轉(zhuǎn)換器2 -或8通道多路復(fù)用器
文件頁(yè)數(shù): 1/13頁(yè)
文件大?。?/td> 202K
代理商: ML2259BCP
May 1997
ML2252
*
, ML2259
**
μP Compatible 8-Bit A/D Converters
with 2- or 8-Channel Multiplexer
GENERAL DESCRIPTION
The ML2252 and ML2259 combine an 8-bit A/D
converter, 2- or 8-channel analog multiplexer, and a
microprocessor compatible 8-bit parallel interface and
control logic in a single monolithic CMOS device.
Easy interface to microprocessors is provided by the
latched and decoded multiplexer address inputs and a
double buffered three-state data bus. These analog-to-
digital converters allow the microprocessor to operate
completely asynchronous to the converter clock.
The built in sample and hold function provides the ability
to digitize a 5V, 50kHz sinewave to 8-bit accuracy. The
differential comparator design provides low power supply
sensitivity to DC and AC variations. The voltage reference
can be externally set to any value between ground and
V
CC
, thus allowing a full conversion over a relatively
small span. All parameters are guaranteed over
temperature with a power supply voltage of 5V ±10%.
The device is suitable for a wide range of applications
from process and machine control to consumer,
automotive, and telecommunication applications.
FEATURES
I
Conversion time (f
CLK
= 1.46MHz); 6.6μs
I
Total unadjusted error; ±1/2LSB or ±1LSB
I
No missing codes
I
Sample and hold; 390ns acquisition
I
Capable of digitizing a 5V, 50kHz sinewave
I
2- or 8-channel input multiplexer
I
0V to 5V analog input range with single 5V
power supply
I
Operates ratiometrically or with up to 5V
voltage reference
I
No zero or full scale adjust required
I
Analog input protection; 25mA per input min
I
Continuous conversion mode
I
Low power dissipation; 15mW max
I
TTL and CMOS compatible digital inputs and outputs
ML2252 BLOCK DIAGRAM
CONTROL
& TIMING
2-CHANNEL
MULTIPLEXER
ADDRESS
LATCH
AND
DECODER
THREE
STATE
OUTPUT
BUFFER
SUCCESSIVE
APPROXIMATION
REGISTER
D/A
CONVERTER
V
CC
A/D WITH
SAMPLE-AND-HOLD FUNCTION
GND
8pF
8pF
Σ
CLOCK
+
+
DB7
COMP
CH0
CH1
ALE
A0
+V
REF
–V
REF
DB6
DB5
DB4
DB3
DB2
DB1
DB0
EOC
START
OE
1
* This Part Is Obsolete
** This Part Is End of Life As Of August 1, 2000
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