參數(shù)資料
型號: ML2009
廠商: Fairchild Semiconductor Corporation
英文描述: μP Compatible Logarithmic Gain/Attenuator(微處理器兼容的對數(shù)增益衰減器)
中文描述: 微處理器兼容的對數(shù)增益/衰減器(微處理器兼容的對數(shù)增益衰減器)
文件頁數(shù): 2/12頁
文件大?。?/td> 70K
代理商: ML2009
ML2008, ML2009
2
REV. 1.0 10/10/2000
PIN CONFIGURATION
NAME
FUNCTION
Negative supply. –5Volts
±
10%
Positive supply. 5Volts
±
10%
Digital ground. 0Volts. All digital
inputs are referenced to this ground.
V
SS
V
CC
GND
AGND
Analog ground. 0Volts. Analog input
and output are referenced to this
ground.
V
IN
V
OUT
D8
Analog input
Analog output
Data bit, ATTEN/
GAIN
D7
Data bit, C3
D6
Data bit, C2
D5
Data bit, C1
D4
Data bit, C0
NAME
FUNCTION
D3
Data bit, F3
D2
Data bit, P
DN
, F2 ML2008; F2 ML2009
Data bit, F0, F1 ML2008; F1 ML2009
D1
D0
Data bit, F0 ML2009 only
WR
Write enable. This input latches the
data bits into the registers on rising
edges of
WR
.
CS
Chip select. This input selects the
device by only allowing the
WR
signal
to latch in data when
CS
is low.
A0
Address select. This input determines
which data word is being written into
the registers.
(ML2008 only)
PIN DESCRIPTION
D7
D6
D5
D4
WR
D3
D2
D1
GND
D8
V
CC
V
OUT
V
SS
AGND
V
IN
NC
CS
A0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TOP VIEW
D8
V
CC
V
OUT
V
SS
AGND
V
IN
NC
CS
D0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TOP VIEW
V
OUT
V
SS
AGND
NC
NC
D4
NC
WR
D3
D2
9
10
11
12
13
D
D
D
D
V
C
D
G
A
C
V
I
4
5
6
7
8
3
2
1
20
19
18
17
16
15
14
TOP VIEW
V
OUT
V
SS
AGND
NC
NC
9
10
11
12
13
D
D
D
D
V
C
D
G
D
C
V
I
4
5
6
7
8
3
2
1
20
19
18
17
16
15
14
TOP VIEW
D4
NC
WR
D3
D2
D7
D6
D5
D4
WR
D3
D2
D1
GND
ML2008
18-Pin DIP (P18)
ML2009
18-Pin DIP (P18)
20-Pin PLCC (Q20)
20-Pin PLCC (Q20)
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