參數(shù)資料
型號(hào): MK60N512VLQ100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, LQFP-144
文件頁數(shù): 51/76頁
文件大?。?/td> 1862K
代理商: MK60N512VLQ100R
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 35. MII signal switching specifications
Symbol
Description
Min.
Max.
Unit
RXCLK frequency
25
MHz
MII1
RXCLK pulse width high
35%
65%
RXCLK
period
MII2
RXCLK pulse width low
35%
65%
RXCLK
period
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
ns
TXCLK frequency
25
MHz
MII5
TXCLK pulse width high
35%
65%
TXCLK
period
MII6
TXCLK pulse width low
35%
65%
TXCLK
period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
25
ns
MII7
MII8
Valid data
MII6
MII5
TXCLK (input)
TXD[n:0]
TXEN
TXER
Figure 22. MII transmit signal timing diagram
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
55
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