- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45330 > MK3732-07SILF (INTEGRATED DEVICE TECHNOLOGY INC) 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 PDF資料下載
參數(shù)資料
| 型號： | MK3732-07SILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 95K |
| 代理商： | MK3732-07SILF |
ADSL VCXO CLOCK SOURCE
MDS 3732-07 F
3
Revision 100102
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
MK3732-07
External Component Selection
The MK3732-07 requires a minimum number of
external components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND on pins 3 and 6, on pins 5 and
6, and on pins 13 and 14, as close to the MK3732-07
as possible. For optimum device performance, the
decoupling capacitors should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and
the loads are over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Quartz Crystal
The MK3732-07 VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters must be used, and
the layout guidelines discussed in the following section
must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3732-07 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3732-07 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3732-07. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
Please see application note MAN05 for recommended
crystal parameters and suppliers.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3732-07 to 3.3V. Connect
pin 4 of the MK3732-07 to the second power supply.
Adjust the voltage on pin 4 to 0V. Measure and record
the frequency of the CLK output.
2. Adjust the voltage on pin 4 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
Error
10
6
x
f
3.3 V
f
tet
arg
–
()
f
0V
f
tet
arg
–
()
+
f
tet
arg
------------------------------------------------------------------------------
error
xtal
–
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK3732-07SILFTR | 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-07SLF | 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-07S | 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-07SLF | 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-09R | 27 MHz, OTHER CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK3732-07SITR | 制造商:ICS 制造商全稱:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-07STR | 制造商:ICS 制造商全稱:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-08 | 制造商:ICS 制造商全稱:ICS 功能描述:ADSL Clock Source |
| MK3732-08R | 功能描述:IC CLOCK SOURCE ADSL 20-QSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| MK3732-08RI | 制造商:ICS 制造商全稱:ICS 功能描述:ADSL Clock Source |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。