參數(shù)資料
型號: MK3724GILFTR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 73.728 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝: 4.4 MM, 0.65 MM PITCH, LEAD FREE, TSSOP-16
文件頁數(shù): 5/8頁
文件大?。?/td> 207K
代理商: MK3724GILFTR
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
VCXO AND SYNTHESIZER
IDT VCXO PLUS AUDIO CLOCK FOR STB
5
MK3724
REV E 051310
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85
° C, unless stated otherwise
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Input High Voltage (S2)
VIH
2.5
V
Input Low Voltage (S1:S0)
VIL
0.8
V
Input Low Voltage (S2)
VIL
0.5
V
Input High Current
IIH
at 3.3V, Sx, PDTS
0.1
A
Input Low Current
IIL
at 0V, Sx, PDTS
-8.5
A
Operating Supply Current
IDD
No load
11
mA
Short Circuit Current
IOS
±50
mA
VIN, VCXO Control Voltage
VIA
03.3
V
On Chip Pull-up Resistor,
inputs
RPU
Input selects
360
k
Input Capacitance
CIN
Input selects
5
pF
Nominal Output Impedance
ZOUT
20
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Crystal Pullability
fP
0V< VIN < 3.3 V, Note 1
+ 100
+ 150
ppm
VCXO Gain
VIN = VDD/2 + 1 V, Note 1
150
ppm/V
Output Rise Time
tOR
20% to 80%, CL=15 pF
1.2
2.0
ns
Output Fall Time
tOF
80% to 20%, CL=15 pF
1.2
2.0
ns
Output Clock Duty Cycle
tD
Measured at 1.65 V, CL=15
pF
40
50
60
%
Maximum Output Jitter,
short term
tJ
CL=15 pF
+150
ps
Changing Frequency
Setting Time
1ms
Power-up time
PLL lock time from power-up
up to ±1% of final frequency
10
ms
PDTS goes high until stable
CLK output up to 1% of final
frequency
2ms
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
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