參數(shù)資料
型號: MK3712DTRLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 27 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 5/6頁
文件大?。?/td> 73K
代理商: MK3712DTRLF
3.3 VOLT SET-TOP BOX VCXO
MDS 3712 B
5
Revision 091801
Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q
w w w. icst . c om
MK3712
DC Electrical Characteristics
VDD=3.3V ±5% , Ambient temperature 0 to +70
°C, unless stated otherwise
AC Electrical Characteristics
VDD = 3.3V ±5%, Ambient Temperature 0 to +70
° C, unless stated otherwise
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
3.45
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
0.4
V
Output High Voltage (CMOS
Level)
VOH
IOH = -4 mA
VDD-0.4
V
Operating Supply Current
IDD
No load
11
mA
Short Circuit Current
IOS
±50
mA
VIN, VCXO Control Voltage
VIA
03.3
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Crystal Pullability
MK3712D
FP
0V< VIN < 3.3V, Note 1
+ 115
ppm
MK3712S
FP
0V< VIN < 3.3V, Note 1
+ 100
ppm
VCXO Gain
MK3712D
VIN = VDD/2 + 1V, Note 1
120
ppm/V
MK3712S
VIN = VDD/2 + 1V, Note 1
140
ppm/V
Output Rise Time
tOR
0.8 to 2.0V, CL=15pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8V, CL=15pF
1.5
ns
Output Clock Duty Cycle
tD
Measured at 1.4V, CL=15pF
40
50
60
%
Maximum Output Jitter,
short term
tJ
CL=15pF
400
ps
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