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參數(shù)資料
| 型號(hào)： | MK3233-02S |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 50 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大小： | 68K |
| 代理商： | MK3233-02S |
MK3233
Handheld System Clock Synthesizer
MDS 3233 F
2
Revision 11070
Printed 11/16/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408) 295-9800 tel www.icst.com
I C R O
C LOC K
Pin Assignment
Number
Name
Type
Description
1
CPUS2
I
Select 2 for CPUCLK frequencies. See Table above.
2
X2
O
Crystal connection. Connect to 32.768 kHz crystal.
3
X1
I
Crystal connection. Connect to 32.768 kHz crystal.
4
VDD32
P
Separate power supply connection for 32.768 kHz clock. Will operate to 2.0 V.
5
VDD
P
Connect to +3.3 V or +5 V. Must be the same voltage as pin 13.
6
GND
P
Connect to ground.
7
COMMCLK
O
Serial communications (1.84 on -01 version, or 3.68MHz on -02 version) clock output.
8
32K
O
32.768 kHz square wave clock output.
9
PDCOMM
I
Power Down serial Communications clock output (stops low) when low.
10
PDCPU
I
Power Down CPU clock output (stops low) when low.
11
PD
I
Powers Down everything but 32 kHz oscillator internally. 32 kHz output buffer is off.
12
GND
P
Connect to ground.
13
VDD
P
Connect to +3.3 V or +5 V. Must be the same voltage as pin 5.
14
CPUCLK
O
CPUCLK output. See Table above.
15
CPUS0
I
Select 0 for CPUCLK frequencies. See Table above.
16
CPUS1
I
Select 1 for CPUCLK frequencies. See Table above.
Pin Descriptions
CPUS2 CPUS1 CPUS0 CPUCLK (MHz)
0
8.00
0
1
13.00
0
1
0
16.00
0
1
20.00
1
0
40.00
1
0
1
25.00
1
0
50.00
1
33.33
CPU Clock Decoding
Type: I = Input, O = output, P = power supply connection
Power Down status: Output clocks will stop in a low state when powered down
1
8
9
16
2
3
4
5
6
7
10
11
12
13
14
15
CPUS1
PDCOMM
PDCPU
CPUCLK
PD
CPUS0
VDD
GND
CPUS2
32K
X2
GND
COMMCLK
VDD32
VDD
X1
External Components
The MK3233 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND, and VDD32 and GND, as close to the
MK3233 as possible. A series resistor should be used on the VDD32 supply. A series termination resistor of
33
may be used for each clock output, except the 32.768 kHz. For tuning the real time clock output, use
a 32.768 kHz crystal with a load capacitance of 12.5pF, and connect a 20pF±5% (NPO dielectric)
capacitor between each crystal pin and ground. The 32.768 kHz crystal must be connected as close to the
chip as possible. Consult MicroClock for a recommended external circuit schematic.
Frequency transitions will occur smoothly.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK3233-02STR | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Handheld System Clock Synthesizer |
| MK3234 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Portable System Clock Synthesizer |
| MK3234-01S | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Portable System Clock Synthesizer |
| MK3234-01STR | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Portable System Clock Synthesizer |
| MK3235 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Handheld System Clock Synthesizer |
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