參數(shù)資料
型號： MK30X256VMD100
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝： 13 X 13 MM, MAPBGA-144
文件頁數(shù)： 13/72頁
文件大?。?/td> 1847K
代理商： MK30X256VMD100
5.3.2 Thermal attributes
Board
type
Symbol
Description
144
LQFP
144
MAPBGA
Unit
Notes
Single-
layer (1s)
RθJA
Thermal resistance, junction to ambient (natural
convection)
52
50
°C/W
Four-layer
(2s2p)
RθJA
Thermal resistance, junction to ambient (natural
convection)
44
30
°C/W
Single-
layer (1s)
RθJMA
Thermal resistance, junction to ambient (200 ft./
min. air speed)
43
41
°C/W
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to ambient (200 ft./
min. air speed)
38
27
°C/W
—
RθJB
Thermal resistance, junction to board
33
17
°C/W
—
RθJC
Thermal resistance, junction to case
11
10
°C/W
—
ΨJT
Thermal characterization parameter, junction to
package top outside center (natural convection)
2
°C/W
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume:
1. output pins
have CL=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
20
Preliminary
Freescale Semiconductor, Inc.
相關PDF資料
PDF描述
MK30X256VMD100R 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
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