參數(shù)資料
型號(hào)： MK30N512VMC100R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 8 X 8 MM, MAPBGA-121
文件頁數(shù)： 11/61頁
文件大小： 1762K
代理商： MK30N512VMC100R
5.3.2 Thermal attributes
Board
type
Symbol
Description
121
MAPBGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal resistance, junction to ambient (natural
convection)
TBD
°C/W
Four-layer
(2s2p)
RθJA
Thermal resistance, junction to ambient (natural
convection)
TBD
°C/W
Single-layer
(1s)
RθJMA
Thermal resistance, junction to ambient (200 ft./min.
air speed)
TBD
°C/W
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to ambient (200 ft./min.
air speed)
TBD
°C/W
—
RθJB
Thermal resistance, junction to board
TBD
°C/W
—
RθJC
Thermal resistance, junction to case
TBD
°C/W
—
ΨJT
Thermal characterization parameter, junction to
package top outside center (natural convection)
TBD
°C/W
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume:
1. output pins
have CL=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
19
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