參數(shù)資料
型號: MK2746-01GLFT
元件分類: 時鐘產(chǎn)生/分配
英文描述: 27 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝: 4.40 MM, 0.65 MM PITCH, TSSOP-16
文件頁數(shù): 3/5頁
文件大?。?/td> 105K
代理商: MK2746-01GLFT
USB-DVR CLOCK SOURCE
MDS 2746 -01 C
3
Revision 041906
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 295-9 800 www.icst.com
MK2746-01
used. To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Crystal Tuning Load Capacitors
For a crystal input, a parallel resonant fundamental
mode crystal should be used. Crystal capacitors must
be connected between each of the pins X1 and X2 to
ground. The value (in pF) of these crystal caps should
equal (CL-6)*2. In this equation CL is equal to the
crystal load capacitance in pF. As an example, for a
crystal with an 18pF load capacitance, each crystal
capacitor would be 24pF [(18-6)*2]=24.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK2746-01.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2746-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
°C
Storage Temperature
-65 to +150
°C
Soldering Temperature
260
°C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
°C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
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MK2746G 功能描述:IC CLK SOURCE DVD/MPEG 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
MK2746GLF 功能描述:IC CLK SOURCE DVD/MPEG 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS,LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP(7x7) 包裝:帶卷 (TR)
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