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參數(shù)資料
| 型號： | MK2705SLFTR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 24.576 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 116K |
| 代理商： | MK2705SLFTR |
Audio Clock Source
MDS 2705 C
3
Revision 102103
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●
www.icst.com
MK2705
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line and as close to the clock output pin as
possible. The nominal impedance of the clock output is
20 .
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK2705 should use one common connection to the
PCB power plane as shown in the diagram on the next
page. The ferrite bead and bulk capacitor help reduce
lower frequency noise in the supply that can lead to
output clock phase modulation.
Recommended Power Supply Connection for
Optimal Device Performance
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(CL - 6) where C is the
load capacitor connected to X1 and X2, and CL is the
specified value of the load capacitance for the crystal.
A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
PCB Layout Recommendations
Observe the following guidelines for optimum device
performance and lowest output phase noise:
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI and obtain the best signal integrity,
the 33
series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK2705. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Connection to3.3V
Power Plane
Ferrite
Bead
Bulk DecouplingCapacitor
(such as 1 FTantalum)
VDDPin
0.01 FDecouplingCapacitors
BothVDDpinsmust beconnectedtothesamevoltage.
相關(guān)PDF資料 |
PDF描述 |
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| MK2731-01GTR | 66.66 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK2742-05STRLF | 40.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2742-04SLF | 81 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2742-06STR | 81 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2742-03STR | 40.5 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2705STR | 功能描述:IC AUDIO CLOCK SOURCE 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK2712 | 制造商:ICS 制造商全稱:ICS 功能描述:NTSC/PAL Clock Source |
| MK2712S | 功能描述:IC CLK SOURCE MTSC/PAL 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2712SLF | 功能描述:時鐘合成器/抖動清除器 NTSC/PAL CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2712SLFTR | 功能描述:時鐘合成器/抖動清除器 NTSC/PAL CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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