參數(shù)資料
型號: MK2308S-2LFTR
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/6頁
文件大小: 0K
描述: IC PLL ZD BUFFER HS 16-SOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 零延遲緩沖器
PLL: 帶旁路
輸入: 時鐘
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133.3MHz
除法器/乘法器: 是/是
電源電壓: 3 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
DATASHEET
ZERO DELAY, LOW SKEW BUFFER
MK2308-2
IDT ZERO DELAY, LOW SKEW BUFFER
1
MK2308-2
REV E 051310
Description
The MK2308-2 is a low jitter, low skew, high performance
Phase-Lock Loop (PLL) based zero delay buffer for high
speed applications. Based on IDT’s proprietary low jitter
PLL techniques, the device provides eight low skew outputs
at speeds up to 133.3 MHz at 3.3 V. The MK2308-2
includes a bank of four outputs running at 1/2X. In the zero
delay mode, the rising edge of the input clock is aligned
with the rising edges of all eight outputs. Compared to
competitive CMOS devices, the MK2308-2 has the lowest
jitter.
Features
Packaged in 16-pin SOIC
Pb (lead) free package
Zero input-output delay
Four 1X outputs plus four 1/2X outputs
Output to output skew is less than 250 ps
Output clocks up to 133.3 MHz at 3.3 V
Ability to generate 2X the input
Full CMOS outputs with 18 mA output drive capability at
TTL levels at 3.3 V
Spread SmartTM technology works with spread spectrum
clock generators
Advanced, low power, sub micron CMOS process
Operating voltage of 3.3 V
Block Diagram
CLKA4
CLKB1
CLKA3
CLKB2
CLKB3
CLKA2
CLKA1
CLKB4
Control
Logic
S2, S1
2
PLL
FBIN
CLKIN
/2
VDD
2
GND
2
BANK
A
BANK
B
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