參數(shù)資料
型號(hào): MK2304S-2ILFTR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁數(shù): 2/6頁
文件大?。?/td> 182K
代理商: MK2304S-2ILFTR
MK2304-2
ZERO DELAY, LOW SKEW BUFFER
ZDB
IDT ZERO DELAY, LOW SKEW BUFFER
2
MK2304-2
REV G 051310
Pin Assignment
Feedback Configuration Table
Pin Descriptions
External Components
The Mk2304-2 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.1
F should be connected between VDD and GND, as close to the part as possible. A 33 series terminating
resistor should be used on each clock output to reduce reflections.
REF
CLKA1
CLKA2
VDD
GND
CLKB2
CLKB1
FBK
1
2
3
4
8
7
6
5
8 Pi n ( 150 mil) SOIC
Feedback From
CLKA1:A2
CLKB1:B2
Bank A
CLKIN
CLKIN/2
Bank B
2XCLKIN
CLKIN
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
REF
Input
Clock input. Connect to input clock source, 5 V tolerant input.
2
CLKA1
Output
Clock A1 output.
3
CLKA2
Output
Clock A2 output.
4
GND
Power
Connect to ground.
5
CLKB1
Output
Clock B1 output.
6
CLKB1
Output
Clock B2 output.
7
VDD
Power
3.3V Power Supply.
8
FBK
Input
PLL feedback input
相關(guān)PDF資料
PDF描述
MK2304S-2LF 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
MK2304S-2 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
MK2308G-1HTR 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK2308S-1HLFT 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK2308G-1HLFT 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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