參數(shù)資料
型號: MK20X256VMB100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA81
封裝: 8 X 8 MM, MAPBGA-81
文件頁數(shù): 14/65頁
文件大?。?/td> 1755K
代理商: MK20X256VMB100
Table 11. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J2
TCLK cycle period
1/J1
ns
J3
TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
20
10
ns
J4
TCLK rise and fall times
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
ns
J6
Boundary scan input data hold time after TCLK rise
0
ns
J7
TCLK low to boundary scan output data valid
25
ns
J8
TCLK low to boundary scan output high-Z
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
ns
J10
TMS, TDI input data hold time after TCLK rise
1
ns
J11
TCLK low to TDO data valid
17
ns
J12
TCLK low to TDO high-Z
17
ns
J13
TRST assert time
100
ns
J14
TRST setup time (negation) to TCLK high
8
ns
Table 12. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
10
20
40
MHz
J2
TCLK cycle period
1/J1
ns
J3
TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
25
12.5
ns
J4
TCLK rise and fall times
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
ns
J6
Boundary scan input data hold time after TCLK rise
0
ns
J7
TCLK low to boundary scan output data valid
25
ns
J8
TCLK low to boundary scan output high-Z
25
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
21
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