參數(shù)資料
型號: MK20DX128ZVMD10R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 52/74頁
文件大?。?/td> 1023K
代理商: MK20DX128ZVMD10R
Table 40. Master mode DSPI timing (low-speed mode) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS6
DSPI_SCK to DSPI_SOUT invalid
-2
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3
DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data
Data
Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 21. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (low-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Frequency of operation
6.25
MHz
DS9
DSPI_SCK input cycle time
8 x tBUS
ns
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
ns
DS13
DSPI_SIN to DSPI_SCK input setup
5
ns
DS14
DSPI_SCK to DSPI_SIN input hold
15
ns
DS15
DSPI_SS active to DSPI_SOUT driven
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
19
ns
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
56
Preliminary
Freescale Semiconductor, Inc.
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