參數(shù)資料
型號： MK20DX128ZVLQ10R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, LQFP-144
文件頁數(shù)： 46/74頁
文件大?。?/td> 1023K
代理商： MK20DX128ZVLQ10R
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACLP Supply current — low-power mode
—
150
μA
IDDA_DACH
P
Supply current — high-speed mode
—
700
μA
tDACLP
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
—
100
200
μs
tDACHP
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
—
15
30
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode and high-speed mode
—
0.7
1
μs
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
100
mV
Vdacouth
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
100
—
VDACR
mV
INL
Integral non-linearity error — high speed mode
—
±8
LSB
DNL
Differential non-linearity error — VDACR > 2 V
—
±1
LSB
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
±1
LSB
VOFFSET
Offset error
—
±0.4
±0.8
%FSR
EG
Gain error
—
±0.1
±0.6
%FSR
PSRR
Power supply rejection ratio, VDDA > = 2.4 V
60
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
TBD
—
ppm of
FSR/C
AC
Offset aging coefficient
—
TBD
μV/yr
Rop
Output resistance load = 3 kΩ
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
High power (SPHP)
Low power (SPLP)
1.2
0.05
1.7
0.12
—
V/μs
CT
Channel to channel cross talk
—
-80
dB
BW
3dB bandwidth
High power (SPHP)
Low power (SPLP)
550
40
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to VDACR100 mV
3. The DNL is measured for 0+100 mV to VDACR100 mV
4. The DNL is measured for 0+100mV to VDACR100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VDACR100 mV
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
50
Preliminary
Freescale Semiconductor, Inc.
相關(guān)PDF資料
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