Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIND
Input leakage current, digital pins
VDD < VIN < 5.5 V
—
1
50
μA
ZIND
Input impedance examples, digital pins
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.5 V
VDD = 1.7 V
—
48
55
57
85
kΩ
RPU
Internal pullup resistors
20
35
50
kΩ
RPD
Internal pulldown resistors
20
35
50
kΩ
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to VDD.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V.
8. Measured at VDD supply voltage = VDD min and Vinput = VSS
9. Measured at VDD supply voltage = VDD min and Vinput = VDD
+
–
Digital input
Source
Z IND
I IND
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode: FEI
General
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
16
Freescale Semiconductor, Inc.