參數(shù)資料
型號: MK2069-01GITR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁數(shù): 11/21頁
文件大小: 411K
代理商: MK2069-01GITR
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
19
MK2069-01
REV K 051310
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may
result in increased output phase noise.
Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the
attempt of the PLL to lock to 0 Hz.
Note 3: The minimum practical input frequency is 1 kHz. Through proper loop filter design lower input frequencies
may be possible.
Note 4: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period.
Note 5: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the
external VCXO PLL loop filter.
Output Rise Time, TCLK
tOR
0.8 to 2.0V, CL=15pF
0.75
1
ns
Output Fall Time, TCLK
tOF
2.0 to 0.8V, CL=15pF
0.75
1
ns
Skew, ICLK to VCLK (Note 5)
tIV
Rising edges, CL=15pF
-5
2.5
+10
ns
Skew, ICLK to RCLK (Note 5)
tIV
Rising edges, CL=15pF
+5
10
+20
ns
Skew, ICLK to TCLK (Note 5)
tVT
Rising edges, CL=15pF
-5
1.5
+10
ns
Nominal Output Impedance
ZOUT
20
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
相關(guān)PDF資料
PDF描述
MK2069-01GI 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILF 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GITR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
MK2069-02GILFTR 160 MHz, OTHER CLOCK GENERATOR, PDSO56
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