參數(shù)資料
型號: MK2059-01SILF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/11頁
文件大?。?/td> 0K
描述: IC VCXO CLK JITTER ATTEN 20-SOIC
標準包裝: 37
類型: 時鐘頻率變換器
PLL:
輸入: LVCMOS
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 25.92MHz
除法器/乘法器: 是/無
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設(shè)備封裝: 20-SOIC
包裝: 管件
其它名稱: 800-2263
MK2059-01SILF-ND
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
6
MK2059-01
REV H 051310
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground,
shown as CL in the External Component Schematic. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no via’s) been the crystal and device.
evaluation. Please refer to application note MAN05 for the
procedure to determine the capacitor values.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed. Please
also refer to the Recommended PCB Layout drawing on
Page 7.
1) Each 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No via’s should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The loop filter components must also be placed close to
the CHGP and VIN pins. CP should be closest to the device.
Coupling of noise from other system signal traces should be
minimized by keeping traces short and away from active
signal traces. Use of vias should be avoided.
3) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
4) To minimize EMI the 33
series termination resistor, if
needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK2059-01. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
The IDT Applications Note MAN05 may also be referenced
for additional suggestions on layout of the crystal section.
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