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參數(shù)資料
| 型號： | MK2049-45SILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK PLL COMM 3.3V 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | PLL 時鐘合成器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 51.84MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
IDT / ICS 3.3 VOLT COMMUNICATIONS CLOCK PLL
6
MK2049-45
REV G 101904
the CHGP and VIN pins. CP should be closest to the device.
Coupling of noise from other system signal traces should be
minimized by keeping traces short and away from active
signal traces. Use of vias should be avoided.
3) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
4) To minimize EMI the 33
series termination resistor, if
needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK2049-45. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
MAN05 may also be referenced for additional suggestions
on layout of the crystal section.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-45. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85
°C
Storage Temperature
-65 to +150
°C
Junction Temperature
125
°C
Soldering Temperature
250
°C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-45SITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK205/100G | 制造商:Fischer Elektronik GmbH & Co KG 功能描述:Bulk |
| MK2058-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock Jitter Attenuator |
| MK205801SI | 制造商:ICS 功能描述: |
| MK2058-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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