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參數(shù)資料
| 型號(hào)： | MK2049-35SI |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | MK2049-35SI |
MK2049-35
3.3 V Communications Clock PLL
MDS 2049-35 B
1
Revision 081401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Packaged in 20 pin SOIC
3.3 V ±5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock,
or 10 to 50 MHz
Locks to 8 kHz ±100 ppm (External mode)
Buffer Mode allows jitter attenuation of
10-50 MHz input and x1/x0.5 or x1/x2 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3,
and OC3 submultiples
See the MK2049-01, -02, and -03 for more
selections at VDD = 5 V, and the MK2049-34 for
more selections at 3.3 V
The MK2049-35 is a Phase-Locked Loop (PLL) based
clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference,
the MK2049-35 generates T1, E1, T3, E3, OC3/3,
Gigabit Ethernet, and other communications
frequencies. This allows for the generation of clocks
frequency-locked to an 8 kHz backplane clock,
simplifying clock synchronization in communications
systems.
This part also has a jitter-attenuated Buffer capability. In
this mode, the MK2049-35 is ideal for filtering jitter
from with high jitter clocks.
ICS can customize these devices for many other
different frequencies. Contact your ICS representative
for more details.
Block Diagram
Description
Features
VDD
GND
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
External/
Buffer Mode
Mux
FS3:0
Clock
Input
CAP1
CAP2
CLK
CLK/2
Output
Buffer
8 kHz
(External
Mode only)
Crystal
Oscillator
Reference
Crystal
X1
X2
4
3
RES
FCAP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-35SITR | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-36SILF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-36SILFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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