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參數(shù)資料
| 型號(hào)： | MK2049-34SI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | MK2049-34SI |
MK2049-34
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
VCXO AND SYNTHESIZER
IDT 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
5
MK2049-34
REV F 102203
PC Board Layout
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins are very
sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two
capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15 and 17,
and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output clocks on pins 8
and 9 should have a series termination of 33
Ω connected close to the pin. Additional improvements will come from keeping
all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away
from the MK2049. You may also refer to application note MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the stray
capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to
much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not adjusted with these
fixed capacitors. However, ICS recommends that the adjustment capacitors be included to minimize the effects of variation
in individual crystals, temperature, and aging. The value of these capacitors (typically 0 - 4 pF) is determined once for a
given board layout, using the procedure found in application note MAN05 on the IDT web site.
16
1
15
2
14
3
13
4
12
5
11
6
7
8
9
10
20
19
18
17
G
cap
resist
cap
ca
p
ca
p
resist
V
G
cap
Optional -
see text
Cutout in ground and power plane.
Route all traces away from this area.
V
= connect to VDD
G
= connect to GND
Figure 2. Typical MK2049-34 Layout
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-34SITR | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2704S | 36.864 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| MK2705S | 24.576 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| MK2716S | 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| MK2727SLF | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
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