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參數(shù)資料
| 型號(hào)： | MK2049-34SI |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 146K |
| 代理商： | MK2049-34SI |
MK2049-34
MDS 2049-34 F
1
Revision 102203
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
3.3 Volt Communications Clock VCXO PLL
Description
The MK2049-34 is a VCXO Phased Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference,
the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL,
and other communications frequencies. This allows for
the generation of clocks frequency-locked and
phase-locked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems. The
MK2409-34 can also accept a T1 or E1 input clock and
provide the same output for loop timing. All outputs are
frequency locked together and to the input.
This part also has a jitter-attenuated Buffer capability.
In this mode, the MK2049-34 is ideal for filtering jitter
from 27 MHz video clocks or other clocks with high
jitter.
ICS can customize these devices for many other
different frequencies.
Features
Packaged in 20-pin SOIC
3.3 V + 5% operation
Fixed I/O phase relationship on all selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4,
and 4E
Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and the OC3 submultiples
See also the MK2049-36 and MK2049-45
Block Diagram
VCXO-BASED
PLL
(MASTER CLOCK
GENERATOR)
EXTERNAL PULLABLE CRYSTAL
(external loop filter)
FREQUENCY
MULTIPLYING
PLL
2
INPUT REFERENCE
CLOCK
(TYPICALLY 8KHZ)
CLOCK OUTPUT
CLOCK OUTPUT / 2
8 KHZ (REGENERATED)
4
FREQUENCY SELECT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-34SITR | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2762-01S | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2762-01STR | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2762-01STR | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2762-01S | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
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